This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-087400, filed Mar. 27, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device (LSI), particularly, to the arrangement and configuration of dummy patterns formed on a semiconductor chip and used in, for example, a logic LSI.
In manufacturing an LSI, it was customary in the past to perform the dimension measurement and management of a mask or a wafer by using dimension measurement marks as a substitute for an actual pattern, i.e., a pattern having a significance as the real circuit.
Also, with progress in the miniaturization of logic LSI products, it is absolutely necessary for the dimension measuring portions (mark positions) to be changed from the portions used in method (a) given below to the portions used in method (b) or (c) given below:
(a) Marks are arranged in the area where patterns are not substantially formed in order to enhance the visual recognition of the marks themselves. As a result, the marks are arranged in positions markedly differing from the actual pattern portions in the pattern density or covering rate.
(b) Marks are arranged in the vicinity of the actual pattern in order to avoid the problem that the marks widely differ from the actual pattern in the density and covering rate.
(c) The actual pattern itself is measured in place of measuring the marks used as a substitute for the actual pattern.
Since the pattern at a fixed portion on the wafer, i.e., the pattern present in the same position on the respective device, is not measured in, particularly, method (b) or (c), required is the specification for the pattern measurement such as drawings and coordination data for every device, with the result that considerable labor and time are consumed for the pattern measurement in accordance with the specification.
Also, in measuring the pattern, much labor is required because it is necessary to find the measuring portions in accordance with the specification. Further, since the required number of pattern measurements is increased with progress in the miniaturization technology, the required labor and time are also increased in accordance with the specification referred to above.
As described above, the problem is inherent in the conventional semiconductor device that, in manufacturing the products, considerable labor and time are required for the pattern measurement in accordance with the specification for the pattern measurement for every device.
An object of the present invention, which has been achieved for overcoming the above-noted problems inherent in the prior art, is to provide a semiconductor device that permits facilitating the operation of dimension measurement and management of the mask or wafer by using a dummy pattern capable of achieving a plurality of objects.
According to a preferred embodiment of the present invention, there is provided a semiconductor device comprising dummy patterns regularly arranged in the entire region or a major portion of an optional wiring layer on a semiconductor chip for controlling the covering rate and the pattern density in the wiring layer in the space between adjacent patterns of the actual pattern, the dummy patterns including dummy patterns for the dimension measurement having dimensions required for the dimension management of the wiring layer and arranged regularly.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.